In a digital data communication system a receiver may receive transmitted data signals that contain errors. A number of factors, such as attenuation of signals, transmission line loss, magnetic field changes, and noise may cause such errors. Various error detection methods have been developed to check received digital data for errors. Linear systematic cyclic codes, commonly known as cyclic redundancy (CRC) codes are typically used to provide error detection capability at various network layers of modern data communications networks.
CRC remainder coefficient generation and checking devices are implemented both in hardware and in software. Typical hardware implementations use serial shifter register schemes wherein feedback shift registers perform a long division of polynomials one bit at a time. To improve throughput, octet algorithms that handle one 8 bit-byte at a time have been developed. These octet algorithms are realized in both hardware and software. However, error processing utilizing CRC computations has a high degree of computational complexity, and thus can have a significant impact on the performance or cost of a digital data communication system. For example, in one application, 1/3 of the processing available from a DSP56156 processor is consumed by CRC computation. Thus, there is a need for an efficient CRC computation device and method that reduces the complexity and processing requirements for CRC computation in a digital data communication system.